diff --git a/src/dmr_flco.c b/src/dmr_flco.c index 4d5cd2e..2c54880 100644 --- a/src/dmr_flco.c +++ b/src/dmr_flco.c @@ -787,7 +787,7 @@ uint8_t dmr_cach (dsd_opts * opts, dsd_state * state, uint8_t cach_bits[25]) if (h1 && h2 && h3 && crc) dmr_slco (opts, state, slco_bits); else { - fprintf (stderr, "\n"); + if (opts->payload == 0) fprintf (stderr, "\n"); fprintf (stderr, "%s", KRED); fprintf (stderr, " SLCO CRC ERR"); fprintf (stderr, "%s", KNRM); diff --git a/src/dmr_le.c b/src/dmr_le.c index 65e7449..e8a9001 100644 --- a/src/dmr_le.c +++ b/src/dmr_le.c @@ -307,9 +307,20 @@ void dmr_sbrc (dsd_opts * opts, dsd_state * state, uint8_t power) //NOTE: on above, I belive that we need to check by opcode as well, as a CRC3 can have multiple collisions //so we need to exclude op/alg 0 and 3 from the check (does algID 0x03/0x23 even exist?) - if (opts->dmr_le == 1) //this will now require a user to switch it on or off until more testing/figuring can be done + if (opts->dmr_le == 1) { - if (irr_err != 0) fprintf (stderr, "\n%s SLOT %d SB/RC (FEC ERR) %d %s \n", KRED, slot, irr_err, KNRM); + if (irr_err != 0) + { + uint32_t sbrcpl = 0; + for(i = 0; i < 32; i++) + { + sbrcpl = sbrcpl << 1; + sbrcpl |= sbrc_interleaved[i] & 1; + } + if (opts->payload == 0) fprintf (stderr, "\n"); + fprintf (stderr, "%s SLOT %d SB/RC (FEC ERR) E:%d; I:%08X D:%03X; %s ", KRED, slot+1, irr_err, sbrcpl, sbrc_hex, KNRM); + if (opts->payload == 1) fprintf (stderr, "\n"); + } if (irr_err == 0) { if (sbrc_hex == 0) ; //NULL, do nothing diff --git a/src/p25p2_vpdu.c b/src/p25p2_vpdu.c index 5155bd7..10ec0c9 100644 --- a/src/p25p2_vpdu.c +++ b/src/p25p2_vpdu.c @@ -1586,7 +1586,7 @@ void process_MAC_VPDU(dsd_opts * opts, dsd_state * state, int type, unsigned lon } //debug - fprintf (stderr, "\n WR: %d TG: %d SRC: %d Res: %d Len: %d STR: %s", wr, ttg, tsrc, res, len, str); + // fprintf (stderr, "\n WR: %d TG: %d SRC: %d Res: %d Len: %d STR: %s", wr, ttg, tsrc, res, len, str); } else