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DMR Stereo TDMA

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DMR Stereo TDMA
--play voice in both TDMA slots with the -T option (dsd -fr -T)
--Improved MS voice (mostly working) and data handling (hit or miss)
--pretty pretty colors on the console log output
--rate 3/4 data decoding partially working
This commit is contained in:
lwvmobile
2022-04-30 04:43:03 -04:00
committed by GitHub
parent 8b48328431
commit 3cd1eefad8
29 changed files with 3291 additions and 1003 deletions
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83
src/dsd_dibit.c
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@@ -185,9 +185,16 @@ use_symbol (dsd_opts* opts, dsd_state* state, int symbol)
}
if (state->dibit_buf_p > state->dibit_buf + 900000)
{
state->dibit_buf_p = state->dibit_buf + 200;
}
{
state->dibit_buf_p = state->dibit_buf + 200;
}
//dmr buffer
if (state->dmr_payload_p > state->dmr_payload_buf + 900000)
{
state->dmr_payload_p = state->dmr_payload_buf + 200;
}
//dmr buffer end
}
static int
@@ -211,6 +218,7 @@ invert_dibit(int dibit)
}
static int digitize (dsd_opts* opts, dsd_state* state, int symbol)
//int digitize (dsd_opts* opts, dsd_state* state, int symbol)
{
// determine dibit state
if ((state->synctype == 6) || (state->synctype == 14)|| (state->synctype == 18))
@@ -252,8 +260,10 @@ static int digitize (dsd_opts* opts, dsd_state* state, int symbol)
return (0); // +1
}
}
else if ((state->synctype == 1) || (state->synctype == 3) || (state->synctype == 5) ||
(state->synctype == 9) || (state->synctype == 11) || (state->synctype == 13) || (state->synctype == 17))
(state->synctype == 9) || (state->synctype == 11) || (state->synctype == 13) ||
(state->synctype == 17) )
{
// 1 -P25p1
@@ -263,7 +273,6 @@ static int digitize (dsd_opts* opts, dsd_state* state, int symbol)
// 11 -DMR (inverted signal voice frame)
// 13 -DMR (inverted signal data frame)
// 17 -NXDN (inverted data frame)
//
int valid;
int dibit;
@@ -361,64 +370,12 @@ static int digitize (dsd_opts* opts, dsd_state* state, int symbol)
}
state->last_dibit = dibit;
//test loading up a shift register and printing it to stderr
//di-bit shift register for hex values
//check for which dibit is equal to which half-nibble
if (dibit == 0){state->hexbuf = 0x0;} //+1
if (dibit == 1){state->hexbuf = 0x1;} //+3
if (dibit == 2){state->hexbuf = 0x2;} //-1
if (dibit == 3){state->hexbuf = 0x3;} //-3
state->sr_0 = (state->sr_0 << 2) | (state->sr_1 >> 62);
state->sr_1 = (state->sr_1 << 2) | (state->sr_2 >> 62);
state->sr_2 = (state->sr_2 << 2) | (state->sr_3 >> 62);
state->sr_3 = (state->sr_3 << 2) | (state->sr_4 >> 62);
state->sr_4 = (state->sr_4 << 2) | (state->sr_5 >> 62);
state->sr_5 = (state->sr_5 << 2) | (state->sr_6 >> 62);
state->sr_6 = state->sr_6 << 2;
state->sr_6 |= state->hexbuf;
if (1 == 2) //disable this later on
{
fprintf (stderr, "\nsr_0 = %16llX \n", state->sr_0);
fprintf (stderr, "sr_1 = %16llX \n", state->sr_1);
fprintf (stderr, "sr_2 = %16llX \n", state->sr_2);
fprintf (stderr, "sr_3 = %16llX \n", state->sr_3);
fprintf (stderr, "sr_4 = %16llX \n", state->sr_4);
fprintf (stderr, "sr_5 = %16llX \n", state->sr_5);
fprintf (stderr, "sr_6 = %16llX \n", state->sr_6);
/*
printw ("sr_0 = %16llX \n", sr_0);
printw ("sr_1 = %16llX \n", sr_1);
printw ("sr_2 = %16llX \n", sr_2);
printw ("sr_3 = %16llX \n", sr_3);
printw ("sr_4 = %16llX \n", sr_4);
printw ("sr_5 = %16llX \n", sr_5);
printw ("sr_6 = %16llX \n", sr_6);
*/
}
if ( state->sr_5 & 0xFFFFF == 0xDDF5D) //disable this later on
{
fprintf (stderr, "\nsr_0 = %16llX \n", state->sr_0);
fprintf (stderr, "sr_1 = %16llX \n", state->sr_1);
fprintf (stderr, "sr_2 = %16llX \n", state->sr_2);
fprintf (stderr, "sr_3 = %16llX \n", state->sr_3);
fprintf (stderr, "sr_4 = %16llX \n", state->sr_4);
fprintf (stderr, "sr_5 = %16llX \n", state->sr_5);
fprintf (stderr, "sr_6 = %16llX \n", state->sr_6);
/*
printw ("sr_0 = %16llX \n", sr_0);
printw ("sr_1 = %16llX \n", sr_1);
printw ("sr_2 = %16llX \n", sr_2);
printw ("sr_3 = %16llX \n", sr_3);
printw ("sr_4 = %16llX \n", sr_4);
printw ("sr_5 = %16llX \n", sr_5);
printw ("sr_6 = %16llX \n", sr_6);
*/
}
*state->dibit_buf_p = dibit;
state->dibit_buf_p++;
//dmr buffer
*state->dmr_payload_p = dibit;
state->dmr_payload_p++;
//dmr buffer end
return dibit;
}
}
@@ -447,9 +404,7 @@ get_dibit_and_analog_signal (dsd_opts* opts, dsd_state* state, int* out_analog_s
//
state->sbuf[state->sidx] = symbol;
//
//state->pulse_raw_out_buffer = symbol;
//
if (out_analog_signal != NULL)
{
*out_analog_signal = symbol;