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Fix DMR FEC/CRC/RAS Implementation Issues;
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@@ -300,7 +300,8 @@ dmr_data_sync (dsd_opts * opts, dsd_state * state)
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info[(2*i) + 99] = (1 & dibit); // bit 0
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}
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dmr_data_burst_handler(opts, state, (uint8_t *)info, burst);
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//don't run on MS Reverse Channel Data
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if (state->dmr_ms_rc == 0) dmr_data_burst_handler(opts, state, (uint8_t *)info, burst);
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//don't run cach on simplex or mono
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if (state->dmr_ms_mode == 0 || opts->dmr_mono == 0)
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